EEE334 Lab_09-1

MOSFET

EEE334

Lab_09-1

MOS Characterizations

Experiment Due Date

Course Professor(s)

The experiment carried out involved characterization of Metal OxideSemiconductor Field Effect Transistor (MOSFET). The main objective ofthe experiment was to enable the student understand the operation ofMOSFET by measuring the current-voltage characteristics to enhancedetermination of N-Channel MOSFET (NMOS) parameters and illustratethe related amplification. Four main procedures were carried out todetermine Vt and kn`W/L of NMOS, roand λ of NMOS, gm of the NMOS transistor and large signaloperation for the transfer characteristics.

The MOSFET parameters were determined by taking data separately forPMOS and NMOS circuits. The characteristics were backed using theequations. The two main circuits used during the experiments arepresented below. To find the characteristics for VT, n andkn VT, p and kp, the gate voltageswere varied and corresponding currents passing through the resistorsmeasured. The output voltages were also recorded. The circuits usedare presented in figure 1 below.

Equipmentand Components

Equipment

Quantity

Model

MOSFET array

1 (contains 3 NMOS and 3 PMOS (P-channel MOSFET) transistors)

CD4007

Digital Multimeter

1

MS8217

Component

Capacitor

1

MOSFET (C-MOS)

1

Diode

1

Course of Action

NMOS circuit results

Vgate

Vdrain

Iresistor (mA)

2.09

0.65

4.329

2.59

0.44

4.539

3.54

0.3

4.679

PMOS results

Vgate

Vdrain

Iresistor (mA)

1.39

4.06

4.072

1.69

3.94

3.952

1.96

3.79

3.801

Using the below equations

…………………………Equation 1a:

……………………………Equation 1b:

………………………………………………………Equation2a:

………………………………………………………Equation 2b:

Then the results are as shown in the table below

NMOS

PMOS

Vt (V)

0.532

-0.463

k (mmho)

5.49

1.03

Below table is a datasheet for the nominal values from manufacturer’sdatasheet for Vt and k.

Vt,min

Vt,typ

Vt,max

kmin

ktyp

NMOS

0.4

0.7

1

5

10

PMOS

-0.4

-0.7

-1.2

2

4

Data Sheet Vt Values

Fromthe table above, the experimental value obtained above fall withinthe standard ranges. Nevertheless, the kp value seems tobe very low, though it is still reasonable.

LTSpice simulation

In determination of Vt and kn`W/L of NMOS, NMOStransistor and ammeter were used. The circuit diagram is as shownbelow.

Thesimulation command was used to generate the results. The commandoperating point helped in generating the data below

Results

From the data above, it was observed that VSD wasequivalent to 4.545 x10-6 V (4.545µV) while VGSwas 5V. On the other hand, the drain current (Id) was 0.00025A(250µA), the reverse bias diode current (Ib) was 5.01 x10-12Aand the source current (Is) was equivalent to -0.00025A (-250µA). Itcan be observed that the drain current and source current are equalbut on the opposite direction.

TransientAnalysis

TheLTSpice was used to simulate the results of the experiment. In thiscase, voltage was varied from zero to 5, using steps of 0.5. Thecircuit diagram for the LTSpice setup is illustrated below.

Thesimulation tool was used to generate the transient values with thestop time at 5, start time at zero and maximum steps were 0.5 each.Then the simulation was run to generate the waveforms as shown in thefigure below.

It can be observed that current (CI) decreases with increase involtage of the load. This trend is typical for semiconductors.Resistance is directly proportional to voltage and inverselyproportional to current. However, for a semiconductor, this does nothold, hence the justification of the trends in the figure above.

Thecomparison for the source, drain and reversed-bias current arepresented in the figure below

Itcan be observed that the Id, Ib and Is remain almost constant withthe changes in load voltage.

Comparison between LTSpice simulation and theoretical(Experimental) data

NMOScharacteristics

From the figure above, the NMOS characteristics seems to match verywell with the SPICE simulation.

Determination of Transfer Characteristics of CMOS Inverter

The transfer characteristics were determined using the sametransistors for the CMOS inverter. The values were then compared withthe theoretical/experimental values and LTSpce model transfercharacteristics. The inverter operations necessary for plotting Vinvs Vout are presented in the figure below.

Inverteroperation regions.

Region A: Cutoff nMOS, linear pMOS hence Vout =Vdd.

Region B:

Expressing this in terms of Vout, Vin and Vddthe equation becomes:

This can be simplified to

Letting

Then.The negative coefficient is+1, yields unrealistic results.

RegionC:

pMOS and nMOS in saturation, hence

The region is vertical due to ignoring the channel length modulation.(Kr= Kn/Kp)

Region D: nMOS, ohmic, pMOS in saturation, hence,

Expressing the equation in terms of Vout, Vinand Vdd

From the quadratic equationthen

The coefficient of willbe -1 positive coefficient provides unrealistic results.

Region E: nMOS ohmic and pMOS off , hence Vout = 0V

Spice Model

*

.model N NMOS (Level=1 Gamma= 0 Xj=0 Tox=1200n Phi=.6

+ Rs=0 Kp=111u Vto=1.2 Lambda=0.01 Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8Cgso=0.1p

+ Cgdo=0.1p Is=16.64p N=1 W=30u L=10u)

*

.model P PMOS (Level=1 Gamma= 0 Xj=0 Tox=1200n Phi=.6

+ Rs=0 Kp=55u Vto=-1.0 Lambda=0.04 Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8Cgso=0.2p

+ Cgdo=0.2p Is=16.64p N=1 W=60u L=10u)

*

The results from SPICE and experiment were transferred to MATLAB andthe values were plotted for experimental, simulation and theoreticalvalues.

InverterTransfer Characteristics.

It can be observed that experimental, simulation and theoreticalcurves tend to relate fairly well.

Discussion

The n-type MOSFET comprises of drain and a source. These are highlyconductiong semiconductor regions of n-type that are normallyisolated from p-type substrate via reversed-bias p-n diode. Mostsemiconducting metal oxides are n-type. This behavior is contributedby the presence of oxygen atoms that are slightly less that the metalions and hence result to weak bounding electrons around the metalions. The weakly bonded electrons enter the conduction band readilymaking the metal oxide become negatively charged. The vacanciesresulting from oxygen makes them become donors to the film. The filmof the MOS becomes interrupted, particularly at the surface. Thisresults in localized energy levels in the energy gap.

MOSFET depends on modulation of the concentration of charge by theMOS capacitance between gate and body electrode insulated by thedielectric oxide layer. The additional terminals (drain and source)in MOSFET connect to the highly doped regions separated by body.Source and drain become highly doped.

Conclusion

The main objective of this experiment was to characterize MOSFET. Theresults obtained in the experiment were very similar to simulatedresults. The current-voltage characteristics were determined and NMOSparameters amplified. As shown in the results, the gate voltage belowvalue of threshold voltage resulted to a lightly populated channelwith small subthreshold leakage current flowing between the drain andthe source.

Thislab experiment provided an opportunity to learn on how the metaloxide semiconductors can be characterized. The experiment was quietinforming as I can now understand the MOSFET operations and amplifythe NMOS.

However, one of the major challenge encountered was in simulationusing the LTSpice and the codes for the model. However, after severalattempts, I manage to simulate and the results were very impressive.I feel that students should be trained thoroughly on simulation, notonly in LTSpice, but also in other software. I found MATLAB to bevery critical when comparing theoretical, experimental and simulatedvalues. Therefore, equipping the students in this department withskills in such software will be critical.

PostLab Questions

  1. From the SPICE results,

Vgate

Vdrain

Iresistor (mA)

rd

2.09

0.65

4.329

0.15015015

2.59

0.44

4.539

0.096937651

3.54

0.3

4.679

0.064116264

  1. A plot of rd vs. VGS is as shown below

  1. In triode region, when VGS &gt Vt, then Id tends to obey ohms law and NMOS transistor will act as a voltage controlled resistor. As the gate voltage increases, MOSFET conduct and develops voltage across it. This makes MOSFET have very high resistance of finite value.

  1. Increasing the value of RD from 2.4kΩ to 100kΩ will enhance reduction in power dissipation and help take advantage of the high input impedance of the MOSFET.

  2. Measurement of threshold voltage, Vtp, and transconductance parameter, kp(W/L) for PMOS transistor.

  1. Connect the circuit as shown in the diagram

  1. Select PMOS on DC4007 chip. Apply a source voltage of 0.5V for VCC and place the ammeter box 1 as shown in the circuit diagram. Increase voltage VCC until the current start flowing. At this point, the transistor will have transitioned from off to on position

  2. Estimate Vtp and add 1k Ohm resistor in series with ammeter.

  3. Use VCC =5V and measure the new voltage between the ground and drain along with the current that flows through the transistor.

  1. Determine Kp using saturation current equation